Bit interleaved data serial interface
US6772251B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Jun 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A shared wire serial interface between two devices that share a system clock and a single bi-directional serial data line. The clock drives both the system and the interface and is provided over a single clock wire. One device operates as a master, the other as a slave. Since master and slave share the same clock, clock drift error will be zero. Although the start of a data transfer is asynchronous with regard to the system clock, the data transfer itself, is synchronous. In one embodiment, the bit transfer rate is ⅛th the system clock speed in one example and is generated by a state machine, however, any divide may be used. The state machine also signals the output enablers which interleave the data bits on the serial data line. The flow of data on a single data line of the interface is bi-directional in that data from the master is bit interleaved with data from the slave. Due to the bit interleaving of data between master and slave, the master can simultaneously shift a command out of its register while shifting in a reply from a previous command. A one bit tri-state period separates each data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.