System and method for optimizing memory bus bandwidth utilization by request classification and ordering
US6772293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | May 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer. Request entries in the write-out section are issued to a system bus only when there are no pending entries in a bus queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.