Method and apparatus for managing out of order memory transactions
US6772300B1 · kind B1 · utility
7Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a computer system is disclosed. The computer system comprises a main memory; and a chip set coupled to the main memory. The chip set comprises a transaction memory, a first bank controller and a second bank controller coupled to the transaction memory. The first bank controller stores transaction data to be transmitted to a first bank of main memory within the transaction memory according to a first linked list. The second bank controller stores transaction data to be transmitted to a second bank of main memory within the transaction memory according to a second linked list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.