ATAPI device unaligned and aligned parallel I/O data transfer controller
US6772311B2 · kind B2 · utility
2Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.