Method and apparatus for optimizing load memory accesses
US6772317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2001 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Nov 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.