Dummy error addition circuit
US6772378B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 9, 2001 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Apr 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/241
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.