Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier
US6773930B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Feb 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28568
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.