Semiconductor integrated circuit device including an ESD protection circuit with an improved ESD protection capability for input or output circuit protection
US6774438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit, an output-signal-fixing circuit and an internal circuit. The output-signal-fixing circuit includes a first capacitor and a second capacitor and fixes an output signal from a second pre-buffer circuit at an “L” level (low voltage) even when an output from the internal circuit is in a floating state. During an ESD test, since an output signal from the second pre-buffer circuit is fixed at an “L” level (low voltage) by the output-signal-fixing circuit, the NMIS transistor is in an OFF state. In this manner, a surge current is prevented from flowing locally into the NMIS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.