Stacked semiconductor package
US6774478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first insulating substrate, a second insulating substrate, and a plurality of semiconductor chip units placed between the first and second insulating substrates. The first insulating substrate has wiring placed on one surface thereof and has first electrically conductive balls which are used as external connection terminals and second electrically conductive balls which radiate heat. The first and second electrically conductive balls are on the other surface thereof. The second insulating substrate is placed opposite to the one surface of the first insulating substrate. Each semiconductor chip unit has a semiconductor chip; a circuit board which has the semiconductor chip mounted thereon and wiring electrically connected to terminals of the semiconductor chip; and a third insulating substrate which is placed on the circuit board and which has a chip cavity for housing the semiconductor chip. By use of the second electrically conductive balls placed on the first insulating substrate, beat generated in the semiconductor chip is efficiently released outside, thus preventing an increase in temperature of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.