Field-programmable gate array architecture
US6774672B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Jan 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located adjacent to an outer edge of the two-by-two array of FPGA tiles. A plurality of boundary scan register chains are located adjacent to an outer perimeter of the two-by-two array of FPGA tiles and the JTAG, Configuration and BIST interfaces. A plurality of RAM blocks are located adjacent to an outer perimeter of the plurality of boundary register scan chains. A plurality of input/output pad rings is located adjacent to an outer perimeter of the plurality of ram blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.