Semiconductor device
US6774674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Sep 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08128
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-potential side power device driving circuit has a clock signal generation circuit generating the so-called internal clock signal by outputting a pulse in a constant cycle for driving NMOS transistors and an iterative pulse generation circuit monitoring the state of an external input signal in synchronization with an output signal of the clock signal generation circuit, receiving a pulsing input signal generated with reference to a ground potential and generating pulsing ON and OFF signals. Thus provided is a level shifting circuit capable of preventing a power device from a malfunction also when a dv/dt transient signal is supplied with time difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.