Dual threshold buffer with hysteresis
US6774676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a buffer having dual thresholds. The buffer has an input terminal and an output terminal and comprises a current source, first through fourth transistors, a current mirror, and an output driver. The buffer uses an “analog” topology to achieve accurate buffering when the thresholds of applied signals are not centered about the mid-supply range. The buffer is useful (among other circuits) in analog and mixed circuit integrated circuits that have relatively high voltage supply levels and signals having logic thresholds that are not centered about the mid-supply level. The buffer uses feedback from the output to achieve hysteresis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.