Semiconductor integrated circuit
US6774679B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit. The semiconductor integrated circuit includes a first circuit for activating a first phase difference signal corresponding to a phase difference between a first clock signal and a second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference sig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.