Level shifter and voltage translator
US6774696B2 · kind B2 · utility
22Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Dec 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.