Current-mode logic differential signal generation circuit employing squelch
US6774700B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electrical circuit generates both a differential data signal and a “squelch,” or “out-of-band,” state over a differential signal pair by employing common-mode logic (CML) technology. In one embodiment of the invention, a CML buffer having true and complementary (inverted) data outputs drive the differential data signal onto the positive (‘p’) and negative (‘n’) signal lines of the differential pair. To implement the squelch state, the true and complementary outputs of a two-input CML multiplexer are coupled with the corresponding outputs of the buffer. The data inputs of the multiplexer are driven by the data input signal driving the buffer, as well as the logical inversion of the data input signal. A squelch state signal then drives an input selector of the multiplexer to impress the squelch state over the differential signal pair when active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.