Fuse trimming failure test circuit for CMOS circuit
US6774702B2 · kind B2 · utility
1Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 3, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Jul 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse trimming failure test circuit for a CMOS circuit includes a first MOS transistor having a source terminal connected to a negative power supply voltage and a gate terminal being connected to a first test signal terminal, a second MOS transistor having a source terminal connected to a positive power supply voltage and a gate terminal connected to a second test signal terminal, a first fuse having one end connected to the drain terminal of the first MOS transistor and a second fuse having one end connected to the drain terminal of the second MOS transistor and another end connected to another end of the first fuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.