System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-PI slip detection
US6774732B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.