Blowable memory device and method of blowing such a memory
US6775175B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.