Memory with shared bit lines
US6775179B2 · kind B2 · utility
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4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and at least one bit line, in which at least two word lines are associated with each row, and at least two adjacent columns share at least one same bit line, two memory cells of the two adjacent columns belonging to a same row being connected to different word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.