Low power state retention
US6775180B2 · kind B2 · utility
35Cited by
1References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.