Data transfer control device and electronic equipment
US6775245B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/2838
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. In addition to a FIFO, an internal RAM capable of storing packets in a randomly accessible manner is provided between a link core and a CPU in a data transfer control device conforming to the IEEE 1394 standard. The RAM storage area is divided into a header area, a data area, and a CPU work area, and the header and data areas are divided into areas for reception and transmission. Tags are used to write the header of a receive packet to the header area and the data thereof to the data area. The data area is divided into areas for isochronous transfer and asynchronous transfer. Pointers are provided for controlling the size of each area in RAM variably, and the size of each area can be varied dynamically after power is switched on. Each area has a ring buffer structure. The size of area storing the header or data of one packet is fixed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.