Digital matched filter
US6775684B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Oct 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital matched filter has a serial-to-parallel conversion circuit that converts input data fed thereto in serial form into n sets of parallel data and a plurality of delay circuits that each output serial data fed thereto with a delay corresponding to n sets of data. The serial-to-parallel conversion circuit and the delay circuits are each fed with n clocks having different phases, and are composed of delay devices connected in n groups of serially connected delay devices so that the input data is shifted in synchronism with the rising edges of those n clocks. The outputs from the individual delay devices are multiplied by codes by multipliers, and the results of those multiplications are added together and output as output data by an adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.