Cache system with limited number of tag memory accesses
US6775741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Feb 19, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.