Method and apparatus for out of order memory processing within an in order processor
US6775756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1999 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.