Chip design method for designing integrated circuit chips with embedded memories
US6775811B2 · kind B2 · utility
2Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.