CMOS devices hardened against total dose radiation effects

US6777753B1 · kind B1 · utility

Assignee

• United States of America as represented by the Secretary of the Air Force · US

Inventors

• Geoffery Summers · Highland, US
• Michael Xapsos · Alexandria, US
• Eric Jackson · Moorpark, US

Key dates

• Filing date: Jul 12, 2000
• Grant date: Aug 17, 2004
• Expiry date: Jul 12, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.