Low stress test mode
US6777969B1 · kind B1 · utility
1Cited by
6References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | May 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2849
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is directed to an apparatus and method for low stress test modes. A method of performing a low stress test mode may include applying an initial voltage in an amount sufficient to perform a device burn-in to a first device and a second device. Voltage at the second device is reduced, wherein voltage is reduced at the second device while voltage at the first device is at an amount sufficient to perform device burn-in.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.