Decoupling capacitor multiplier
US6778004B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A decoupling circuit comprising a first capacitor, and a first current mirror coupled to the capacitor, wherein the first current mirror is configured to multiply the capacitance effect of the first capacitor is disclosed. The first current mirror may comprise a first transistor, and a second transistor coupled to the first transistor, wherein the second transistor is configured to amplify the current entering the first transistor. The first transistor and the second transistor may comprise n-channel MOSFET transistors. The decoupling circuit may further comprise a bias network coupled to the first current mirror, wherein the bias network is configured to bias the first current mirror. The bias network may comprise a p-channel MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.