Display operation with inserted block clears
US6778155B2 · kind B2 · utility
195Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0266
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An SLM PWM clocking method, called “jog clear,” for generating short bit periods where block data clears (74) are inserted between block data loads (72, 76) within a frame refresh period. The method significantly reduces the short bit duration that requires use of the earlier reset-release method and it eliminates undesirable artifacts present in these earlier SLM clocking methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.