Semiconductor memory device and method of manufacturing the same
US6778424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2001 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Dec 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer (12), a source region (15) formed in the semiconductor layer, a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (13) provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate (20) provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate. The MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.