Receiver architecture employing low intermediate frequency and complex filtering
US6778594B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator. Although a low IF is not generally understood to promote the image rejection performance of a receiver, substantial image rejection is afforded by the polyphase filter, thereby enabling the receiver to be realized almost entirely as a monolithic integrated semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.