Digital transceiver with multi-rate processing
US6778599B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03509
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital data receiver includes a front end, coupled to receive an input signal transmitted over a communication channel, the signal representing a stream of transmitted symbols with a given input symbol rate, and to generate, responsive to the input signal, a stream of received samples at a processing rate that is a non-integer rational multiple of the input symbol rate. A feed-forward equalizer receives input samples at the processing rate, responsive to the received samples, and generates forward-equalized samples at the input symbol rate. Decision circuitry processes the forward-equalized samples so as to generate a stream of estimated symbols at the input symbol rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.