Wide shift array structure with low-voltage excursion sensing
US6779007B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital shifter apparatus features an n-bit wide shifter configured as a two-dimensional array of n2 bit pass-through cells placed at substantially regular intervals within the array in n rows of n columns each, and plural low-voltage swing (LVS) sense amplifiers coupled with the n rows for sensing a low-voltage excursion bit value corresponding with a shifted digital output. Preferably, each of the plural bit storage cells includes a complementary pair of transistor gates producing a differential output signal pair representing a datum shifted into the corresponding cell. However, in a wide shift array, the heavy load on the differential multiplexor (mux) output makes the signal develop slowly, which results in only a small differential signal (e.g. approximately 100 mV) in a high-speed shift operation. The use of a small signal sense amplifier overcomes the problem mentioned above. In accordance with the invention, n such sense amplifiers are coupled with n corresponding differential output signal pairs, with each of the n sense amplifiers being responsive to a low-voltage-swing differential output signal pair to produce a high-voltage digital output signal compatible with norm…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.