Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains
US6779096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2001 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Oct 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock. The first predetermined phase offset and the second predetermined phase offset are adjustable based on performance characteristics of the first subsystem and performance characteristics of the second subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.