Method and apparatus for processing compressed VLIW subinstruction opcodes
US6779101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Mar 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An area of on-chip memory is allocated to store one or more tables of commonly-used opcodes. The normal opcode in the instruction is replaced with a shorter code identifying an index into the table. As a result, the instruction is compressed. For a VLIW architecture, in which an instruction includes multiple subinstructions (multiple opcodes), the instruction loading bandwidth is substantially reduced. Preferably, an opcode table is dynamically loaded. Different tasks are programmed with a respective table of opcodes to be stored in the opcode table. The respective table is loaded when task switching. A smaller, dynamic opcode table provides an effective selection and a low table loading overhead
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.