Two pipeline stage microprocessor and method for processing an instruction
US6779105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | May 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a pipeline microprocessor (MP) comprising a first pipeline stage (ST1) comprising means IPC, MMU, PC, B2, DEC1) for reading and decoding instructions (CODEOP, ADRs, ADRd) of a program recorded in a memory (MEM), and a second pipeline stage (ST2), contiguous to the first pipeline stage, comprising two sectors (ST21, ST22) activated one after the other during complementary half-cycles of a clock signal (H1) of the microprocessor. The first sector reads data contained in two registers (Rd, Rs) of a bank of registers (BANK1, BANK2) of the microprocessor and carries out an operation on the data according to an instruction (CODEOP, ADRs, ADRd) received at the previous clock cycle. The second sector (ST22) comprises means (B4, DEC1) to record the result of the operation in a register of the bank of registers (BANK1, BANK2). Application especially to chip cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.