Thinned semiconductor wafer and die and corresponding method
US6780733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer (10) having integrated circuit elements formed therein is thinned and a first carrier (41) is adhered thereto. The first carrier (41) facilitates handling of the thinned wafer (30). A second carrier (51) is then adhered as well and the various integrated circuits are singulated to yield a plurality of thinned die (81). Once the thinned die is mounted to a desired substrate (91), the first carrier (41) is readily removed. In one embodiment, the first carrier (41) has an adhesive that becomes less adherent when exposed to a predetermined stimulus (such as a given temperature range or a given frequency range of photonic energy). Such thinned die (or modules containing such die) are readily amenable to stacking in order to achieve significantly increased circuit densities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.