Packaging substrate for electronic elements and electronic device having packaged structure
US6781221B2 · kind B2 · utility
6Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate for electronic elements comprises a first area for receiving an electronic element through flip chip bonding and a second area for receiving an electronic element through wire bonding. The first area has a bonding pad having applied on a surface thereof a coating of a solder material. The packaging substrate is used in the production of an electronic device having mounted thereon electronic elements such as semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.