Low-frequency auto-zeroed amplifier
US6781450B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2003 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45753
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is related to glitch reduction of the output of an auto-zero amplifier. The auto-zero amplifier may be used in a voltage regulator, and the glitch reduction in the auto-zero amplifier will result in reduced output ripple. The auto-zero amplifier stores an input offset during an auto-zero phase, so that the input offset can be corrected during an amplification phase. During the amplification phase, the gate-drain voltage of a first transistor is sampled onto a capacitor. During the auto-zero phase, the capacitor is used to maintain the same voltage across the gate-drain voltage of the first transistor that was present during the amplification phase. The capacitor maintains the gate-drain voltage during the auto-zero phase in order to compensate for the large step in voltage that would otherwise occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.