Low power low voltage differential signal receiver with improved skew and jitter performance
US6781460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45192
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.