Tunable oscillator
US6781470B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7176
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oscillator includes a common logic circuit and a plurality of delay lines. Each delay line is configured to receive a state transition at its input terminal and to output a corresponding state transition at its output terminal after a corresponding delay. An output terminal of each delay line is in electrical circuit with a corresponding input terminal of the common logic circuit, and the input terminal of each of the delay lines is in selectable electrical circuit with the output terminal of the common logic unit. The common logic circuit is configured to output a state transition at its output terminal in response to a state transition at any one of the input terminals of the common logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.