Defects detection
US6781897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Aug 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector. Embodiments of apparatus for carrying out the methods of the invention are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.