TDM bus synchronization circuit and protocol and method of operation
US6782007B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5675
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
There is disclosed a data transfer system that uses a TDM serial multiple format and supporting method that is capable of multiplexing and de-multiplexing a number of asynchronous and arbitrarily framed component serial data streams. The data transfer system comprises: 1) a frame data interface circuit capable of receiving incoming data streams from a plurality of asynchronous frame data sources and indicating their frame boundaries with the bit streams; and 2) a transmit buffer and data segmenter coupled to the frame data interface circuit and receiving the incoming data frames therefrom. The transmit buffer/segmenter divides incoming data frames into N-bit data fields and attaches to each N-bit data field an M-bit control field identifying the frame bit boundary and capable of conveying additional control or synchronization information associated with the incoming data frames. Each N-bit data field and the attached M-bit control field comprise a data record to be transmitted. The data records are assembled into a TDM transport formatted datagram consisting of, for example, 28 time slots, each of which is capable of carrying a single data record from a selected serial buffer/segme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.