Device for spatially and temporally reordering for data between a processor, memory and peripherals
US6782435B2 · kind B2 · utility
31Cited by
19References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Sep 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.