Mapping a logical address to a plurality on non-logical addresses
US6782464B2 · kind B2 · utility
4Cited by
10References
87Claims
0Family size
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Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Communication between different entities of a computing environment is facilitated by an address mapping capability. Messages are sent between the entities to have desired tasks performed. Instead of providing within the messages the actual non-logical addresses (e.g., virtual, real addresses) used to perform the tasks, logical addresses are provided. The logical addresses are then mapped to the non-logical addresses. Each logical address can map to a plurality of non-logical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.