Operand queues for streaming data: A processor register file extension
US6782470B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2000 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The programmer determines the trade-off between the number and size of the operand queue(s) versus the number of registers used for the program. The programmer partitions a portion of the registers into one or more operand queues. A given queue occupies a consecutive set of registers, although multiple queues need not occupy consecutive registers. An additional address bit is included to distinguish operand queue addresses from register addresses. Queue state logic tracks status information for each queue, including a header pointer, tail pointer, start address, end address and number of vacancies value. The program sets the locations and depth of a given operand queue within the register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.