IC layout system having separate trial and detailed routing phases
US6782520B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.