Semiconductor device having wide wiring pattern in outermost circuit
US6782522B2 · kind B2 · utility
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1References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Nov 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor electronic part, having a lot of bumps allocated in a checkered pattern, is solder-mounted on a multilayer circuit board. In the multilayer circuit board, a first wiring pattern linked with a first land is finer than a second wiring pattern linked with a second land. Only one first wiring pattern is passable between lands. The second lands are allocated in the outmost line on the uppermost layer of the multilayer circuit board. In the semiconductor electronic part, bumps connectable with the second lands are allocated in the outermost line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.