Method of protecting a passivation layer during solder bump formation
US6782897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Aug 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.