Package structure and method for making the same
US6784020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/974
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MFMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.